LTC2208UP-14
FEATURES
Sample Rate: 160Msps
77.3dBFS Noise Floor
100dB SFDR
SFDR >84dB at 250MHz (1.5VP-P Input Range)
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
700MHz Full Power Bandwidth S/H
Optional Internal Dither
Optional Data Output Randomizer
LVDS or CMOS Outputs
Single 3.3V Supply
Power Dissipation: 1.45W
Clock Duty Cycle Stabilizer
Pin-Compatible Family:
130Msps: LTC2208 (16-Bit), LTC2208-14 (14-Bit)
105Msps: LTC2217 (16-Bit)
64-Pin (9mm × 9mm) QFN Package
APPLICATIONS
Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
ATE
DESCRIPTION
LTC2208-141220814fb14-Bit, 130Msps ADCThe LTC®2208-14 is a 130Msps, sampling 14-bit A/D converter designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 700MHz. The input range of the ADC can be optimized with the PGA front end.
The LTC2208-14 is perfect for demanding communications applications, with AC performance that includes 77.1dBFS Noise Floor and 98dB spurious free dynamic range (SFDR). Ultralow jitter of 70fsRMS allows undersampling of high input frequencies with excellent noise performance. Maximum DC specs include ±1.5LSB INL, ±0.5LSB DNL (no missing codes).
The digital output can be either differential LVDS or single-ended CMOS. There are two format options for the CMOS outputs: a single bus running at the full data rate or demultiplexed buses running at half data rate. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V.
The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer al-lows high performance at full speed with a wide range of clock duty cycles. |